Reconfigurable and scalable architecture of a system for digital processing of broadband radar signals

Abstract

A reconfigurable and scalable architecture of systems for digital processing and synthesis of broadband radar signals is studied. The design of a radar with this architecture and a bandwidth of the synthesized and processed signals of 1.5 GHz is considered. The potential to adjust the radar parameters independently on the basis of the system-level analysis of the architecture and by working over the issues of its implementation is demonstrated. The architecture relies on specialized methods for digital signal processing with programmable logic and parallel processing.