Providing Reliability of Physical Systems: Fully Delay Testable Logical Circuit Design with Compact Representation of all PDF Test Pairs

Abstract

Functional reliability is one of the important properties of physical systems provided by reliability of system components, in particular, control logical components. The new approach to fully delay testable circuit design oriented to cut overheads and lengths of circuit paths has been developed. Compact representation of all PDF test pairs is reduced to keeping the corresponding generative vector pairs. The number of generative vector pairs does not exceed the doubled number of internal ROBDD nodes originating from the circuit, while the number of the circuit paths can exponentially depend on the number of these internal nodes. The algorithm of involving the PDF test pair from the proper generative vector pair is suggested. This procedure does not require essential calculations. The algorithm of deriving the generative vector pair has a polynomial complexity.