Email this article Computing Observability of Gates in Combinational Logic Circuits by Bit-Parallel Simulation
- Authors: Telpukhov D.V.1, Nadolenko V.V.2, Gurov S.I.3
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Affiliations:
- Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
- Institute for Design Problems in Microelectronics (IPPM RAS)
- Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
- Issue: Vol 30, No 2 (2019)
- Pages: 177-190
- Section: Article
- URL: https://ogarev-online.ru/1046-283X/article/view/247865
- DOI: https://doi.org/10.1007/s10598-019-09445-y
- ID: 247865
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Abstract
The article considers vector computation methods (bit-parallel simulation) for determining the observability of combinational logic gates. The computations produce an ODC (observability don’t care) set of all gates for a given set of circuit states. These results make it possible to evaluate the probability of logical masking of a random circuit fault. The methods are compared by accuracy and time costs using testing results for ISCAS ’85 benchmark circuits.
About the authors
D. V. Telpukhov
Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
Author for correspondence.
Email: nofrost@inbox.ru
Russian Federation, Moscow
V. V. Nadolenko
Institute for Design Problems in Microelectronics (IPPM RAS)
Email: nofrost@inbox.ru
Russian Federation, Moscow
S. I. Gurov
Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
Email: nofrost@inbox.ru
Russian Federation, Moscow
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